SpacemiT V100: A 46-Core RISC-V Server CPU for Linux

RISC-V just took a big step toward the data center. SpacemiT, the company behind the K1 and K3 chips that power a growing list of RISC-V single board computers and mini PCs, has detailed the V100, a 46-core server processor developed with China's open-source XiangShan CPU team. LinuxGizmos covered the announcement on October 19, 2026, and SpacemiT's own product brief calls it the first RISC-V CPU that fully meets the RISC-V server specification requirements.

• Cores: 6 XiangShan Kunminghu V2R2 cores at up to 2.1GHz plus 40 SpacemiT X100 cores at up to 2.4GHz, 64MB system-level cache
• Memory and I/O: 8 channels of DDR5-4800 (307GB/s, up to 2TB per socket) and 52 PCIe 5.0 lanes
• Platform: 12nm, 120W TDP, RVA23 profile, up to 92 cores in a dual-socket server
• Software: Ubuntu, Debian, Fedora, Red Hat, Rocky Linux and openEuler listed as supported distributions

What Is Inside the SpacemiT V100?

The V100 uses a hybrid layout. The six Kunminghu V2R2 cores are the heavy hitters: a 13-stage, six-issue out-of-order pipeline with 1MB of private L2 cache each. The 40 X100 cores use a 12-stage, four-issue out-of-order design with 2MB of shared L2 cache and dynamic frequency scaling. SpacemiT's brief quotes per-core SPECint2006 targets of at least 15.0 per GHz for Kunminghu and 9.0 per GHz for X100. Both core types support the RVA23 profile, the hypervisor extension and 256-bit vector instructions, including vector cryptography.

On memory, eight DDR5 RDIMM channels deliver a stated 307GB/s of peak bandwidth with sideband ECC. That is a serious figure for a RISC-V part, and it is exactly what AI inference and database workloads crave. The 52 PCIe 5.0 lanes leave room for NVMe storage, fast networking and accelerator cards.

Why Does RISC-V Server Spec Compliance Matter?

This is the real headline. Until now, booting Linux on a RISC-V board usually meant a vendor kernel and a board-specific image. The V100 is designed to comply with the RISC-V Server SoC Specification, the Server Platform Specification and the Boot and Runtime Services specification, with a firmware stack built on UEFI, ACPI, SMBIOS and OpenSBI. According to LinuxGizmos, SpacemiT says the chip has passed architecture, SoC and firmware compliance tests, so supported distributions can boot without platform-specific changes, and KVM virtualization works through the upstream kernel.

That is the same "it just works" story that made Arm servers practical. It also complements the desktop side of the ecosystem, where projects like the Ubuntu 26.10 RISC-V desktop images for SpacemiT K3 are maturing fast.

Three Reference Servers

SpacemiT is pairing the chip with three designs, per LinuxGizmos:

• C2201 Compute Server: 2U, single or dual socket, up to 92 cores, 4TB of DDR5, 12 U.2 NVMe bays and dual 25GbE
• G5201 Intelligent Computing Server: 4U with room for eight full-height, dual-width accelerator cards and 400Gbps RDMA networking
• S5236 Storage Server: 24 to 64 drive bays, with the 36-bay version holding roughly 619TB raw

Pricing and availability have not been announced, so this is one to watch rather than order. Still, for homelab builders and RISC-V fans who have followed the jump from tiny boards to 16-core SpacemiT K3 mini PCs, a standards-compliant server chip is a big milestone. More in our mini computers section.

Sources: LinuxGizmos — Server-class 46-core RISC-V CPU runs mainstream Linux — October 19, 2026; SpacemiT — V100 Brief (product documentation) — October 2026.