Clintech Pico Unlocks All 48 GPIOs on Raspberry Pi's RP2354B for Just $20
Clintech's $20 Pico-compatible board is the first to use the RP2354B chip variant, exposing all 48 GPIO pins alongside dual ARM and RISC-V cores for embedded developers.
Every GPIO Pin, Finally Exposed: The Clintech Pico RP2354B
The Raspberry Pi RP2350 family introduced a significant jump in capability over its RP2040 predecessor — dual-core ARM Cortex-M33 processors with an optional RISC-V mode, substantially more memory, and hardware-accelerated cryptography. But the standard Pico 2, using the RP2350A die, exposes only 26 of the chip's available GPIO pins through its standard pinout. For embedded developers who need more I/O capacity, that ceiling is a genuine limitation.
Clintech Ltd. has released what appears to be the first development board built on the RP2354B — the chip variant that exposes the full complement of 48 GPIOs. Published on CNX Software on March 19, 2026, the Clintech Pico puts all of that GPIO headroom into a Pico-compatible board for just $20 on Tindie, shipped worldwide from Bulgaria.
What Makes the RP2354B Different
The RP2354B is a larger die variant of the RP2350 family. It retains the same dual-core ARM Cortex-M33 and dual-core RISC-V Hazard3 architecture running at 150 MHz, but adds a substantially larger I/O footprint. Where the RP2350A (used in Pico 2) exposes 26 GPIOs through the standard Pico pinout, the RP2354B has 48 total GPIO pins available.
The Clintech Pico exposes 40 of these GPIOs through two 20-pin headers arranged in the standard Pico layout, with the remaining GPIO connections — including the QSPI interface — accessible through castellated pads and through-holes on the board. This design preserves drop-in compatibility for Pico 2 footprints while making the additional I/O reachable for projects that genuinely need it.
Dual-Core, Dual-Architecture Programming
One of the more interesting capabilities enabled by the RP2354B is mixed-architecture operation. The chip can run ARM Cortex-M33 code on one core and RISC-V Hazard3 code on the other simultaneously — or run both cores as ARM, or both as RISC-V, depending on the application. This flexible architecture makes the Clintech Pico a low-cost entry point for developers interested in exploring RISC-V development without committing to dedicated RISC-V hardware.
Memory, Storage, and Connectivity
The board ships with 520 KB of on-chip SRAM and 2 MB of stacked QSPI flash, expandable to 16 MB through the accessible QSPI interface or swapped for PSRAM for applications requiring high-bandwidth memory access. A USB Type-C port handles programming and power, and a three-pin SWD debug header supports hardware debug workflows.
Physical dimensions are 51 × 21 mm — the same width as the standard Pico — which preserves breadboard compatibility and makes it a straightforward upgrade for projects that have exhausted the standard Pico's GPIO count.
Filling a Real Gap in the Pico Ecosystem
The Pico ecosystem has matured significantly since the original Pico launched in 2021, but the constraint of 26 exposed GPIOs has required workarounds — GPIO expanders, I2C multiplexers, or choosing entirely different hardware — for projects needing more I/O. The Clintech Pico eliminates that constraint at the same price point as the problem it solves, making it one of the more practically useful Pico-family additions in recent memory.
Sources: [CNX Software](https://www.cnx-software.com) (March 19, 2026), [Tindie](https://www.tindie.com) (March 2026)